USB Cheat Sheet (2022)
I spend time investigating a non-existing bug today because I misunderstood a USB term. So I made myself a cheat sheet. Maybe it will save time to someone.
USB Gen A x B
A = Generation
B = Num lanes used
Note: Multi-lanes systems, uses lane striping (on TX) and lane bonding (on RX).
a - What they put on the box.
b - Rate with encoding overhead. e.g, 8b/10b = 20%.
c - Real life sequencial read rate.
4 wires: PWR, GND, D+, D-.
8 wires: PWR, GND, D+, D-. RX+ , RX- , TX- , TX+.
12 wires: PWR, GND, D+, D-, RX1+, RX1-, RX2-, RX2+, TX1+, TX1-, TX2-, TX2+.
Note: 1 USB lane = 1 twisted wire pair +/-.
Note: 4 wires = 1 half-duplex lane, 8 wires = 2 lanes (one up, one down), and 12 wires = 4 lanes (two up, two down).
| Type-A 4-wires | Type-A 8-wires | Type-B 4-wires | Type-B 8-wires |
|---|---|---|---|
 |
 |
 |
 |
Only the USB Type-C connector has enough pins to support two lanes.
| Specifications | Max. Voltage | Max. Current | Max. Power |
|---|---|---|---|
| USB 2.0 | 5V | 500mA | 2.5W |
| USB 3.0 / USB3.1 | 5V | 900mA | 4.5W |
| USB Battery Charging (BC) 1.2 | 5V | 1.5A | 7.5W |
| USB-C Current Mode (non-PD) | 5V | 3A | 15W |
| USB-C / Power Delivery (PD 1/2) | 20V | 5A | 100W |
| USB-C PD 3.1 (EPR) | 48V | 5A | 240W |
USB 1.0 (Jan, 1996).
USB 1.1 (Sep, 1998).
USB 2.0 (Apr, 2000).
USB 3.0 (Nov, 2008).
USB 3.1 (Jul, 2013).
USB 3.2 (Sep, 2017).
USB 4.0 (Aug, 2019).
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